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[VHDL-FPGA-Verilog] uart_verilog

Description: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Platform: | Size: 9216 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] sopc

Description: altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
Platform: | Size: 8863744 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] uart from opencores

Description: 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Platform: | Size: 9216 | Author: 熊明 | Hits:

[Communication] 曼彻斯特码

Description: 今天看了一下从fpga上下的曼彻斯特编解码的程序，感觉不是很清楚，仿真了一下，更迷茫了，大家看看为啥这程序要这么编呢？ 程序比较长，不过写的应该还是不错的，看了后应该有收获。 总的思路是这样： 1 通过一个高频的时钟检测wrn信号，如果检测到上升沿，则表明开始编码，将输入的8位数据转为串行，并编码，然后输出。 2 定时信号是从高频时钟16分频后得到的，在wrn上升沿后16分频使能，在编码结束后禁止分频输出。 3 no_bits_sent记录串行输出的位数，应该是从0010到1001输出串行信号，到1010时编码结束，输出tbre表明编码完成。 问题是no_bits_sent在到了1010后还是会继续增加，直到1111，然后clk1x_enable 就为0，无法分频，clk1x就为一直流信号。这样当clk1x_enable再次为1的时候，no_bits_sent也不会增加，在1111上不变，clk1x_enable又会回到0了。 -today they simply watched from across the Manchester encoding and decoding process, not feeling very well, simulation a bit more confused, we look at procedures to be ready this series so? Procedures longer, but should still write good, it should have read harvest. The thinking is this : one by a high-frequency clock signal detection international, if detected rising edge, it indicates the beginning of coding will be entered into the eight to serial data and coding, and then output. Two timing signals from the high-frequency clock frequency 16 hours after the the international rising edge after 16 minutes frequency to enable the coding after the end of Prohibition-frequency output. 3 no_bits_sent record median serial output, it should be from 0010 to 1001 serial output signal to the end of
Platform: | Size: 5120 | Author: 游畅 | Hits:

[Embeded-SCM Develop] board_diag

Description: 在fpga上关于nios开发版的测试文件，测试对象包括led,lcd，uart,内存，基本io等，对于检测硬件十分有用-they simply on the development of the nios version of the test document, including testing led, LCD, UART, memory, basic io, for the very useful hardware detection
Platform: | Size: 8192 | Author: wp | Hits:

[Other Embeded program] UART_BooQuai

Description: FPGA上实现UART串口原程序，在ISE6编写的-FPGA serial UART to achieve the original procedure, the preparation of the ISE6
Platform: | Size: 11264 | Author: 樊 | Hits:

[VHDL-FPGA-Verilog] Altera_uart_VHDL

Description: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA/CPLD applications, UART communications VHDL source.
Platform: | Size: 10240 | Author: cyberworm | Hits:

[VHDL-FPGA-Verilog] Altera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[VHDL-FPGA-Verilog] FPGAUART

Description: 一个基于FPGA的串口程序,已经经过验证,对用FPGA做串口的朋友提供参考和借鉴!-an FPGA-based serial procedures have proven, right Serial do with FPGA reference for a friend and borrow!
Platform: | Size: 311296 | Author: 舟舟 | Hits:

[VHDL-FPGA-Verilog] uartvhdl

Description: 一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
Platform: | Size: 10240 | Author: 王利 | Hits:

[VHDL-FPGA-Verilog] UART_ise7_bak

Description: 用FPGA 实现全双工异步串口（UART），与PC 机通信。1 位起始位；8 位数据位；一个停止位；无校验位；波特率为2400、4800、9600、11520 任选或可变（可用按键控制波特率模式）。-using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,4800,9600, 11520 optional or variable (baud rate can be used to control keypad mode).
Platform: | Size: 32768 | Author: lee | Hits:

[Other] PCI_Bridge_Guest_UART

Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Platform: | Size: 8427520 | Author: heartbeat | Hits:

[Books] Quartus-guide

Description: quartus的教程，是初学者使用FPGA的好老师，介绍了quartus的使用方法，并且有例子-quartus curricula, the use of FPGA beginners is a good teacher. quartus introduced the use, and is an example
Platform: | Size: 1183744 | Author: mh | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: 简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20-Simplified serial communication, removing the parity bit, the baud rate to 9600, test, fpga model xinlinx vp20
Platform: | Size: 5120 | Author: 刘红亮 | Hits:

[VHDL-FPGA-Verilog] VHDLserial

Description: UART参考设计带缓存用于Xinlix用于FPGA-UART reference design with cache for Xinlix for FPGA
Platform: | Size: 279552 | Author: sd | Hits:

[Software Engineering] FPGAUART

Description: 用VHDl设计UART的文章，使用QuartusII平台-Design with VHDL UART article, use QuartusII platform
Platform: | Size: 136192 | Author: 胡玉贵 | Hits:

[source in ebook] fpga_uart

Description: 基于FPGA 实现异步串口可以值得参考。-Asynchronous FPGA-based serial port can be worth considering.
Platform: | Size: 10240 | Author: chenwei | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] uart

Description:
Platform: | Size: 14336 | Author: 顾向南 | Hits:

[MPI] UART_Download

Description: 此为FPGA上的一个串口通信程序，已经通过仿真测试，完全可行-This is the FPGA a serial communication program has been tested through simulation, entirely feasible
Platform: | Size: 9216 | Author: 王骏 | Hits:
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